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CA5160 Scheda tecnica(PDF) 6 Page - Intersil Corporation

Il numero della parte CA5160
Spiegazioni elettronici  4MHz, BiMOS Microprocessor Operational Amplifier with MOSFET Input/CMOS Output
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Produttore elettronici  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CA5160 Scheda tecnica(HTML) 6 Page - Intersil Corporation

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6
Second Stage
Most of the voltage gain in the CA5160 is provided by the
second amplifier stage, consisting of bipolar transistor Q11
and its cascode-connected load resistance provided by
PMOS transistors Q3 and Q5. The source of bias potentials
for these PMOS transistors is described later. Miller Effect
compensation (roll off) is accomplished by means of the 30pF
capacitor and 2k
Ω resistor connected between the base and
collector of transistor Q11. These internal components provide
sufficient compensation for unity gain operation in most
applications. However, additional compensation, if desired,
may be used between Terminals 1 and 8.
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R2
and zener diode Z1 serve to establish a voltage of 8.3V across
the series connected circuit, consisting of resistor R1, diodes
D1 through D4, and PMOS transistor Q1. A tap at the junction
of resistor R1 and diode D4 provides a gate bias potential of
about 4.5V for PMOS transistors Q4 and Q5 with respect to
Terminal 7. A potential of about 2.2V is developed across
diode connected PMOS transistor Q1 with respect to Terminal
7 to provide gate bias for PMOS transistors Q2 and Q3. It
should be noted that Q1 is “mirror connected” to both Q2 and
Q3. Since transistors Q1, Q2 and Q3 are designed to be
identical, the approximately 200
µA current in Q1 establishes a
similar current in Q2 and Q3 as constant current sources for
both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener diode
Z1 becomes non-conductive and the potential, developed
across series connected R1, D1-D4, and Q1 varies directly
with variations in supply voltage. Consequently, the gate bias
for Q4, Q5 and Q2, Q3 varies in accordance with supply
voltage variations. This variation results in deterioration of the
power supply rejection ration (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about
4.5V results in seriously degraded performance.
Output Stage
The output stage consists of a drain loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 20. Typical op-amp
loads are readily driven by the output stage. Because large
signal excursions are nonlinear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
Offset Nulling
Offset voltage nulling is usually accomplished with a 100,000
potentiometer connected across Terminals 1 and 5 and with the
potentiometer slider arm connected to Terminal 4. A fine offset
null adjustment usually can be affected with the slider arm
positioned in the mid point of the potentiometer’s total range.
Input Current Variation with Common Mode Input
Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA5160 Series Op Amps is typically 5pA at
TA = 25
oC when Terminals 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal 4.
Figure 1 contains data showing the variation of input current
as a function of common-mode input voltage at TA =25
oC.
These data show that circuit designers can advantageously
exploit these characteristics to design circuits which typically
require an input current of less than 1pA, provided the
common-mode input voltage does not exceed 2V. As
previously noted, the input current is essentially the result of
the leakage current through the gate-protection diodes in the
input circuit and, therefore, a function of the applied voltage.
Although the finite resistance of the glass terminal-to-case
insulator of the metal can package also contributes an
increment of leakage current, there are useful compensating
factors. Because the gate-protection network functions as if
it is connected to Terminal 4 potential, and the metal can
case of the CA5160 is also internally tied to Terminal 4, input
terminal 3 is essentially “guarded” from spurious leakage
currents.
Input Current Variation with Temperature
The input current of the CA5160 series circuits is typically
5pA at 25oC. The major portion of this input current is due to
leakage current through the gate protective diodes in the
input circuit. As with any semiconductor-junction device,
including op amps with a junction-FET input stage, the
10
7.5
5
2.5
0
-1
01234567
INPUT CURRENT (pA)
TA = 25
oC
15V
TO
5V
V+
V-
0V
TO
-10V
CA5160
2
3
6
7
8
4
PA
VIN
FIGURE 1. CA5160 INPUT CURRENT vs COMMON MODE
VOLTAGE
CA5160


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