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AD8328ACP-EVAL Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD8328ACP-EVAL Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 20 page AD8328 Rev. A | Page 4 of 20 1 TOKO 458 PT-1087 used for above specifications. Typical insertion loss of 0.3 dB @ 10 MHz. 2 Guaranteed by design and characterization to ±4 sigma for TA = 25°C. 3 Measured through a 2:1 transformer. 4 Specification is worst case over all gain codes. 5 Guaranteed by design and characterization to ±3 sigma for TA = 25°C. 6 VIN = 29 dBmV, QPSK modulation, 160 kSPS symbol rate. LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V; full temperature range. Table 2. Parameter Min Typ Max Unit Logic 1 Voltage 2.1 5.0 V Logic 0 Voltage 0 0.8 V Logic 1 Current (VINH = 5 V) CLK, SDATA, DATEN 0 20 nA Logic 0 Current (VINL = 0 V) CLK, SDATA, DATEN –600 –100 nA Logic 1 Current (VINH = 5 V) TXEN 50 190 μA Logic 0 Current (VINL = 0 V) TXEN −250 −30 μA Logic 1 Current (VINH = 5 V) SLEEP 50 190 μA Logic 0 Current (VINL = 0 V) SLEEP −250 −30 μA TIMING REQUIREMENTS Full temperature range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Clock Pulse Width (tWH) 16.0 ns Clock Period (tC) 32.0 ns Setup Time SDATA vs. Clock (tDS) 5.0 ns Setup Time DATEN vs. Clock (tES) 15.0 ns Hold Time SDATA vs. Clock (tDH) 5.0 ns Hold Time DATEN vs. Clock (tEH) 3.0 ns Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF) 10 ns |
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