NBSG53A

http://onsemi.com

2

VTD

CLK

CLK

VTCLK

R

VTCLK

D

D

VTD

SEL

OLS

Q

Q

A

B

C

D

12

3

4

Figure 1. BGA−16 Pinout (Top View)

VTD

D

D

VTD

R

SEL OLS

Q

Q

VTCLK

CLK

CLK

VTCLK

56

7

8

16

15

14

13

12

11

10

9

1

2

3

4

NBSG53A

Exposed Pad

(EP)

Figure 2. QFN−16 Pinout (Top View)

Table 1. Pin Description

Pin

Name

I/O

Description

BGA

QFN

C2

1

VTCLK

−

Internal 50

W Termination Pin. See Table 4.

C1

2

CLK

ECL, CML,

LVCMOS,

LVDS, LVTTL

Input

Inverted Differential Input.

B1

3

CLK

ECL, CML,

LVCMOS,

LVDS, LVTTL

Input

Noninverted Differential Input.

B2

4

VTCLK

−

Internal 50

W Termination Pin. See Table 4.

A1

5

VTD

−

Internal 50

W termination pin. See Table 4.

A2

6

D

ECL, CML,

LVCMOS,

LVDS, LVTTL

Input

Inverted Differential Input.

A3

7

D

ECL, CML,

LVCMOS,

LVDS, LVTTL

Input

Noninverted Differential Input.

A4

8

VTD

−

Internal 50

W Termination Pin. See Table 4.

D1,B3

9,16

−

Positive Supply Voltage

B4

10

Q

RSECL Output

NonInverted Differential Output. Typically Terminated with 50

W Resistor to

C4

11

Q

RSECL Output

Inverted Differential Output. Typically Terminated with 50

W Resistor to

C3

12

−

Negative Supply Voltage

D4

13

OLS*

Input

Input Pin for the Output Level Select (OLS). See Table 2.

D3

14

SEL

LVECL,

LVCMOS,

LVTTL Input

Select Logic Input. Internal 75 k

D2

15

R

LVECL,

LVCMOS,

LVTTL Input

Reset D Flip−Flop. Internal 75 k

N/A

−

EP

Exposed Pad. (Note 1)

package bottom (see case drawing) must be attached to a heat−sinking conduit.

2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination volt-

age, and if no signal is applied then the device will be susceptible to self−oscillation.