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NBSG16VSMN Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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NBSG16VSMN Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 14 page NBSG16VS http://onsemi.com 2 Figure 1. BGA−16 Pinout (Top View) VEE D D VTD VEE VBB VTD NC VCTRL VEE VCC VCC VMM VEE Q Q A B C D 12 3 4 VEE NC VCTRL VEE VEE VBB VMM VEE VCC Q Q VCC VTD D D VTD 56 7 8 16 15 14 13 12 11 10 9 1 2 3 4 NBSG16VS Exposed Pad (EP) Figure 2. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description BGA QFN C2 1 VTD − Internal 50 W Termination Pin. See Table 2. C1 2 D ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Internal 75 k W to VEE and 36.5 kW to VCC. B1 3 D ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted Differential Input. Internal 75 k W to VEE. B2 4 VTD − Internal 50 W Termination Pin. See Table 2. A1,D1,A4, D4 5,8,13,16 VEE − Negative Supply Voltage A2 6 NC − No Connect A3 7 VCTRL Output Amplitude Swing Control. Bypass Pin to VCC through 0.1 mF Capacitor. B3,C3 9,12 VCC − Positive Supply Voltage B4 10 Q RSECL Output Noninverted Differential Output. Typically Terminated with 50 W to VTT = VCC − 2 V C4 11 Q RSECL Output Inverted Differential Output. Typically Terminated with 50 W to VTT = VCC − 2 V D3 14 VMM − LVCMOS Reference Voltage Output. (VCC − VEE)/2 D2 15 VBB − ECL Reference Voltage Output N/A − EP − Exposed Pad. (Note 2) 1. The NC pin is electrically connected to the die and must be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat−sinking conduit. 3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. |
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