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74F163ASJ Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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74F163ASJ Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 11 page ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74F161A, 74F163A Rev. 1.0.2 2 Logic Symbols Unit Loading/Fan Out 74F161A IEEE/IEC 74F161A 74F163A IEEE/IEC 74F163A Pin Names Description U.L. HIGH / LOW Input IIH / IIL Output IOH / IOL CEP Count Enable Parallel Input 1.0 / 1.0 20µA / -0.6mA CET Count Enable Trickle Input 1.0 / 2.0 20µA / -1.2mA CP Clock Pulse Input (Active Rising Edge) 1.0 / 1.0 20µA / -0.6 mA MR (74F161A) Asynchronous Master Reset Input (Active LOW) 1.0 / 1.0 20µA / -0.6 mA SR (74F163A) Synchronous Reset Input (Active LOW) 1.0 / 2.0 20µA / -1.2 mA P0–P3 Parallel Data Inputs 1.0 / 1.0 20µA / -0.6 mA PE Parallel Enable Input (Active LOW) 1.0 / 2.0 20µA / -1.2mA Q0–Q3 Flip-Flop Outputs 50 / 33.3 -1mA / 20mA TC Terminal Count Output 50 / 33.3 -1mA / 20mA |
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