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MC14553BDW Scheda tecnica(PDF) 5 Page - ON Semiconductor |
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MC14553BDW Scheda tecnica(HTML) 5 Page - ON Semiconductor |
5 / 8 page MC14553B http://onsemi.com 5 OPERATING CHARACTERISTICS The MC14553B three−digit counter, shown in Figure 4, consists of three negative edge−triggered BCD counters which are cascaded in a synchronous fashion. A quad latch at the output of each of the three BCD counters permits storage of any given count. The three sets of BCD outputs (active high), after going through the latches, are time division multiplexed, providing one BCD number or digit at a time. Digit select outputs (active low) are provided for display control. All outputs are TTL compatible. An on−chip oscillator provides the low frequency scanning clock which drives the multiplexer output selector. The frequency of the oscillator can be controlled externally by a capacitor between pins 3 and 4, or it can be overridden and driven with an external clock at pin 4. Multiple devices can be cascaded using the overflow output, which provides one pulse for every 1000 counts. The Master Reset input, when taken high, initializes the three BCD counters and the multiplexer scanning circuit. While Master Reset is high the digit scanner is set to digit one; but all three−digit select outputs are disabled to prolong display life, and the scan oscillator is inhibited. The Disable input, when high, prevents the input clock from reaching the counters, while still retaining the last count. A pulse shaping circuit at the clock input permits the counters to continue operating on input pulses with very slow rise times. Information present in the counters when the latch input goes high, will be stored in the latches and will be retained while the latch input is high, independent of other inputs. Information can be recovered from the latches after the counters have been reset if Latch Enable remains high during the entire reset cycle. Figure 4. Expanded Block Diagram PULSE SHAPER CLOCK 12 11 DISABLE (ACTIVE HIGH) C R Q0 Q1 Q2 Q3 ÷10 UNITS C R Q0 Q1 Q2 Q3 ÷10 TENS C R Q0 Q1 Q2 Q3 ÷10 HUNDREDS 10 LATCH ENABLE QUAD LATCH QUAD LATCH QUAD LATCH R R SCAN OSCILLATOR SCANNER PULSE GENERATOR C1 4 3 C1A C1B MULTIPLEXER 9 7 6 5 Q0 Q1 Q2 Q3 BCD OUTPUTS (ACTIVE HIGH) 13 14 21 15 MR (ACTIVE HIGH) OVERFLOW DS1DS2DS3 (LSD) DIGIT SELECT (MSD) (ACTIVE LOW) |
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