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MC14538BDG Scheda tecnica(PDF) 5 Page - ON Semiconductor |
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MC14538BDG Scheda tecnica(HTML) 5 Page - ON Semiconductor |
5 / 12 page MC14538B http://onsemi.com 5 Figure 1. Logic Diagram (1/2 of DevIce Shown) NOTE: Pins 1, 8 and 15 must be externally grounded − + − + VDD VDD P1 RX CX 2 1 (14) (15) 4 (12) 5(11) 3 (13) A B RESET VSS N1 Vref1 C1 C2 ENABLE Vref2 ENABLE CONTROL S RESET LATCH QR QR R S R S Q Q 6(10) 7(9) OUTPUT LATCH Figure 2. Power Dissipation Test Circuit and Waveforms 500 pF VDD 0.1 mF CERAMIC RX RX′ CX′ VSS CX VSS Vin CX/RX A B RESET A′ B′ RESET′ Q Q Q′ Q′ VSS CL CL CL CL 20 ns 20 ns VDD 0 V 90% 10% Vin ID INPUT CONNECTIONS Characteristics Reset A B tPLH, tPHL, tTLH, tTHL, T, tWH, tWL VDD PG1 VDD tPLH, tPHL, tTLH, tTHL, T, tWH, tWL VDD VSS PG2 tPLH(R), tPHL(R), tWH, tWL PG3 PG1 PG2 Figure 3. Switching Test Circuit *Includes capacitance of probes, wiring, and fixture parasitic. NOTE: Switching test waveforms for PG1, PG2, PG3 are shown In Figure 4. VDD RX RX′ VSS CX CX/RX A B RESET A′ B′ RESET′ Q Q Q′ Q′ CL CX′ CL CL CL VSS PULSE GENERATOR PULSE GENERATOR PULSE GENERATOR VSS *CL = 50 pF PG1 = PG2 = PG3 = |
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