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MC14536BDWR2G Scheda tecnica(PDF) 8 Page - ON Semiconductor |
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MC14536BDWR2G Scheda tecnica(HTML) 8 Page - ON Semiconductor |
8 / 14 page MC14536B http://onsemi.com 8 Figure 8. Power Dissipation Test Circuit and Waveform Figure 9. Switching Time Test Circuit and Waveforms VDD 0.01 mF CERAMIC 500 mF ID CL CL CL VSS PULSE GENERATOR SET RESET 8−BYPASS IN1 C INH MONO−IN OSC INH C B A D OUT 1 OUT 2 DECODE OUT 20 ns 20 ns 90% 10% 50% 50% DUTY CYCLE PULSE GENERATOR SET RESET 8−BYPASS IN1 C INH MONO−IN OSC INH C B A D OUT 1 OUT 2 DECODE OUT CL VSS VDD 20 ns 20 ns 50% IN1 tWL tWH 50% tPHL 90% 10% tPLH tTLH tTHL OUT FUNCTIONAL TEST SEQUENCE Test function (Figure 10) has been included for the reduction of test time required to exercise all 24 counter stages. This test function divides the counter into three 8−stage sections and 255 counts are loaded in each of the 8−stage sections in parallel. All flip−flops are now at a “1”. The counter is now returned to the normal 24−stages in series configuration. One more pulse is entered into In1 which will cause the counter to ripple from an all “1” state to an all “0” state. Figure 10. Functional Test Circuit VDD VSS PULSE GENERATOR SET RESET 8−BYPASS IN1 C INH MONO−IN OSC INH C B A D OUT 1 OUT 2 DECODE OUT FUNCTIONAL TEST SEQUENCE Inputs Outputs Comments In1 Set Reset 8−Bypass Decade Out Q1 thru Q24 All 24 stages are in Reset mode. 1 0 1 1 0 1 1 1 1 0 Counter is in three 8 stage sections in parallel mode. 0 1 1 1 0 First “1” to “0” transition of clock. 1 0 − − − 1 1 1 255 “1” to “0” transitions are clocked in the counter. 0 1 1 1 1 The 255 “1” to “0” transition. 0 0 0 0 1 Counter converted back to 24 stages in series mode. Set and Reset must be connected together and simultaneously go from “1” to “0”. 1 0 0 0 1 In1 Switches to a “1”. 0 0 0 0 0 Counter Ripples from an all “1” state to an all “0” state. |
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