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MC14532BCPG Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC14532BCPG Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2006 April, 2006 − Rev. 6 1 Publication Order Number: MC14532B/D MC14532B 8−Bit Priority Encoder The MC14532B is constructed with complementary MOS (CMOS) enhancement mode devices. The primary function of a priority encoder is to provide a binary address for the active input with the highest priority. Eight data inputs (D0 thru D7) and an enable input (Ein) are provided. Five outputs are available, three are address outputs (Q0 thru Q2), one group select (GS) and one enable output (Eout). Features • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load over the Rated Temperature Range • Pb−Free Packages are Available* MAXIMUM RATINGS (Voltages Referenced to VSS) Rating Symbol Value Unit DC Supply Voltage Range VDD −0.5 to +18.0 V Input or Output Voltage Range (DC or Transient) Vin, Vout −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin Iin, Iout ±10 mA Power Dissipation, per Package (Note 1) PD 500 mW Ambient Temperature Range TA −55 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Lead Temperature (8 Sec Soldering) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. TRUTH TABLE Input Output Ein D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 Eout 0 X X X X X X X X 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 X X X X X X X 1 1 1 1 0 1 0 1 X X X X X X 1 1 1 0 0 1 0 0 1 X X X X X 1 1 0 1 0 1 0 0 0 1 X X X X 1 1 0 0 0 1 0 0 0 0 1 X X X 1 0 1 1 0 1 0 0 0 0 0 1 X X 1 0 1 0 0 1 0 0 0 0 0 0 1 X 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 X = Don’t Care *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOIC−16 D SUFFIX CASE 751B MARKING DIAGRAMS http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ORDERING INFORMATION A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week G = Pb−Free Package 14532BG AWLYWW PDIP−16 P SUFFIX CASE 648 1 1 MC14532BCP AWLYYWWG 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 D2 D3 GS Eout VDD Q0 D0 D1 D7 D6 D5 D4 VSS Q1 Q2 Ein PIN ASSIGNMENT 1 1 |
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