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MC14517BDWR2 Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC14517BDWR2 Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 6 page © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 6 1 Publication Order Number: MC14517B/D MC14517B Dual 64−Bit Static Shift Register The MC14517B dual 64−bit static shift register consists of two identical, independent, 64−bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data input is entered by clocking, regardless of the state of the write enable input. An output is disabled (open circuited) when the write enable input is high. During this time, data appearing at the data input as well as the 16−bit, 32−bit, and 48−bit taps may be entered into the device by application of a clock pulse. This feature permits the register to be loaded with 64 bits in 16 clock periods, and also permits bus logic to be used. This device is useful in time delay circuits, temporary memory storage circuits, and other serial shift register applications. Features • Diode Protection on All Inputs • Fully Static Operation • Output Transitions Occur on the Rising Edge of the Clock Pulse • Exceedingly Slow Input Transition Rates May Be Applied to the Clock Input • 3−State Output at 64th−Bit Allows Use in Bus Logic Applications • Shift Registers of any Length may be Fully Loaded with 16 Clock Pulses • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range • Pb−Free Packages are Available* MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Symbol Value Unit DC Supply Voltage Range VDD −0.5 to +18.0 V Input or Output Voltage Range (DC or Transient) Vin, Vout −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin Iin, Iout ±10 mA Power Dissipation per Package (Note 1) PD 500 mW Operating Temperature Range TA −55 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Lead Temperature (8−Second Soldering) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Device Package Shipping† ORDERING INFORMATION MC14517BCP PDIP−16 25 Units/Rail MC14517BDW SOIC−16 47/Rail MC14517BDWR2 SOIC−16 1000/Tape & Reel http://onsemi.com MC14517BDWR2G SOIC−16 (Pb−Free) 1000/Tape & Reel MC14517BDWG SOIC−16 (Pb−Free) 47/Rail MC14517BCPG PDIP−16 (Pb−Free) 25 Units/Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package MARKING DIAGRAMS PDIP−16 P SUFFIX CASE 648 16 1 MC14516BCP AWLYYWWG 1 SOIC−16 DW SUFFIX CASE 751G 16 1 14517B AWLYYWWG 1 PIN ASSIGNMENT 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 CB WEB Q48B Q16B VDD DB Q32B Q64B CA WEA Q48A Q16A VSS Q32A Q64A DA |
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