© Semiconductor Components Industries, LLC, 2006

June, 2006 − Rev. 12

1

Publication Order Number:

MC100LVEP210/D

MC100LVEP210

2.5V / 3.3V1:5 Dual

Differential ECL/PECL/HSTL

Clock Driver

Description

The MC100LVEP210 is a low skew 1−to−5 dual differential driver,

designed with clock distribution in mind. The ECL/PECL input

used. The signal is fanned out to 5 identical differential outputs. HSTL

inputs can be used when the EP210 is operating in PECL mode.

The LVEP210 specifically guarantees low output−to−output skew.

Optimal design, layout, and processing minimize skew within a device

and from device to device.

To ensure the tight skew specification is realized, both sides of the

differential output need to be terminated identically into 50

W even if

only one output is being used. If an output pair is unused, both outputs

may be left open (unterminated) without affecting skew.

The MC100LVEP210, as with most other ECL devices, can be

LVEP210 to be used for high performance clock distribution in +3.3 V

or +2.5 V systems. Single−ended CLK input operation is limited to a

Designers can take advantage of the LVEP210’s performance to

distribute low skew clocks across the backplane or the board. In a

PECL environment, series or Thevenin line terminations are typically

used as they require no additional power supplies. For more

information on using PECL, designers should refer to Application

Note AN1406/D.

Features

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

32−LEAD LQFP

FA SUFFIX

CASE 873A

MARKING

DIAGRAM*

A

= Assembly Location

WL

= Wafer Lot

YY

= Year

WW

= Work Week

G= Pb−Free Package

http://onsemi.com

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

MC100

LVEP21

AWLYYWWG