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CAT28C257L-15T Scheda tecnica(PDF) 1 Page - Catalyst Semiconductor |
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CAT28C257L-15T Scheda tecnica(HTML) 1 Page - Catalyst Semiconductor |
1 / 12 page 1 ADDR. BUFFER & LATCHES ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION CONTROL LOGIC TIMER ROW DECODER COLUMN DECODER HIGH VOLTAGE GENERATOR A7–A14 CE OE WE A0–A6 I/O0–I/O7 I/O BUFFERS 32,768 x 8 EEPROM ARRAY 128 BYTE PAGE REGISTER VCC DATA POLLING AND TOGGLE BIT CAT28C257 256K-Bit CMOS PARALLEL EEPROM FEATURES ■ Fast read access times: 120/150 ns ■ Low power CMOS dissipation: –Active: 25 mA max. –Standby: 150 µA max. ■ Simple write operation: –On-chip address and data latches –Self-timed write cycle with auto-clear ■ Fast write cycle time: –5ms max ■ CMOS and TTL compatible I/O ■ Automatic page write operation: –1 to 128 Bytes in 5ms –Page load timer ■ End of write detection: –Toggle bit – DATA DATA DATA DATA DATA polling ■ Hardware and software write protection ■ 100,000 Program/erase cycles ■ 100 Year data retention ■ Commercial, industrial and automotive temperature ranges DESCRIPTION The CAT28C257 is a fast, low power, 5V-only CMOS Parallel EEPROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto- clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self- timed write cycle. Additionally, the CAT28C257 features hardware and software write protection. The CAT28C257 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP or 32-pin PLCC packages. BLOCK DIAGRAM © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 1015, Rev. D ALO GEN FR TM LEAD FREE |
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