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CAT24C0A1PI-1.8TE13 Scheda tecnica(PDF) 4 Page - Catalyst Semiconductor

Il numero della parte CAT24C0A1PI-1.8TE13
Spiegazioni elettronici  1K-Bit Serial EEPROM
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Produttore elettronici  CATALYST [Catalyst Semiconductor]
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Logo CATALYST - Catalyst Semiconductor

CAT24C0A1PI-1.8TE13 Scheda tecnica(HTML) 4 Page - Catalyst Semiconductor

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Discontinued
Part
CAT24C01B
4
Doc. No. 1081, Rev. E
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FUNCTIONAL DESCRIPTION
The CAT24C01B uses a 2-wire data transmission pro-
tocol. The protocol defines any device that sends data to
the bus to be a transmitter and any device receiving data
to be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24C01B
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24C01B serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
SDA: Serial Data/Address
The CAT24C01B bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wired with other
open drain or open collector outputs.
2-WIRE BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
Figure 3. Start/Stop Timing
5020 FHD F05
5020 FHD F04
5020 FHD F03
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL


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