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MC100LVEL32DG Scheda tecnica(PDF) 4 Page - ON Semiconductor |
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MC100LVEL32DG Scheda tecnica(HTML) 4 Page - ON Semiconductor |
4 / 8 page MC100LVEL32 http://onsemi.com 4 Table 5. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 7) Symbol Characteristic −40°C 25°C 85°C Unit Min Typ Max Min Typ Max Min Typ Max fmax Maximum Toggle Frequency 2.2 2.5 2.4 2.6 2.6 2.8 GHz tPLH tPHL Propagation Delay CLK to Q (Differential) CLK to Q (Single−Ended) Reset to Q 350 300 440 500 500 555 530 580 640 370 320 450 510 510 540 550 600 650 410 360 480 540 540 580 590 640 680 ps tRR Reset Recovery 175 50 175 50 175 50 ps tPW Minimum Pulse Width Reset 500 300 500 300 500 300 ps tJITTER Random Clock Jitter (RMS) 2.0 2.0 2.0 ps VPP Input Swing (Differential Swing) (Note 8) 150 1000 150 1000 150 1000 mV tr tf Output Rise/Fall Times Q (20% − 80%) 120 225 320 120 225 320 120 225 320 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. VEE can vary ±0.3 V. 8. VPP(min) is input swing measured single−ended on each input in differential configuration. Figure 1. Timing Diagram CLK RESET Q Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Driver Device Receiver Device QD Q D Zo = 50 W Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V |
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