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MC100EL39DWR2G Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC100EL39DWR2G Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 7 page MC100EL39 http://onsemi.com 2 CLK Figure 1. Pinout: SOIC−20 (Top View) CLK MR VCC 17 18 16 15 14 13 12 4 3 5678 9 Q0 11 10 Q1 Q1 Q2 Q2 Q3 Q3 VEE EN 19 20 2 1 VCC Q0 VBB VCC NC NOTE: All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. CLK CLK EN MR DIVSELb P2/4 Q0 Q0 Q1 Q1 P4/6 Q2 Q2 Q3 Q3 Figure 2. Logic Diagram R R DIVSELa Table 1. PIN DESCRIPTION Pin Function CLK, CLK EN MR Q0, Q0; Q1, Q1 Q2, Q2; Q3, Q3 DIVSELa, DIVSELb VBB VCC VEE NC ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Diff ÷2/4 Outputs ECL Diff ÷4/6 Outputs ECL Frequency Select Input ECL Frequency Select Input Reference Voltage Output Positive Supply Negative Supply No Connect Table 2. FUNCTION TABLE Function CLK* EN* MR* Divide Hold Q0−3 Reset Q0−3 Z ZZ X L H X L L H Z = Low-to-High Transition ZZ = High-to-Low Transition *Pin will default low when left open. DIVSELa** Q0, Q1 Outputs 0 1 Divide by 2 Divide by 4 DIVSELb** Q2, Q3 Outputs 0 1 Divide by 4 Divide by 6 **Pin will default low when left open. |
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