TL1466I

HIGHSPEED/PRECISION SIX CHANNEL

SWITCHING REGULATOR CONTROLLER

SLVS262 − FEBRUARY 2000

4

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

DESCRIPTION

NAME

NO.

DESCRIPTION

BOOT CAP.H−1

44

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 1.

BOOT CAP.L−1

45

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 1.

BOOT CAP.H−2

48

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 2.

BOOT CAP.L−2

49

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 2.

BOOT CAP.H−3

54

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 3

BOOT CAP.L−3

55

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 3

BOOT CAP.L−4

58

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 4.

BOOT CAP.H−4

59

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 4.

BOOT CAP.L−5

1

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 5.

BOOT CAP.H−5

2

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 5.

BOOT CAP.L−6

5

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 6.

BOOT CAP.H−6

6

Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 6.

COMP

13

Output regulation voltage monitor terminal. When this terminal voltage drops below VREF voltage (1.5 V),

charging to capacitor connected to SCP terminal (pin 23) is initiated.

COMP−1

40

Output regulation voltage monitor terminal (channel 1). When this terminal voltage drops below VREF voltage

(1.5 V) charging to capacitor connected to SCP terminal (pin 23) is initiated.

COMP−2

37

Output regulation voltage monitor terminal (channel 2). When this terminal voltage drops below VREF voltage

(1.5 V) charging to capacitor connected to SCP terminal (pin 23) is initiated.

COMP−3

34

Output regulation voltage monitor terminal (channel 3). When this terminal voltage drops below VREF voltage

(1.5 V), charging to capacitor connected to SCP terminal (pin 23) is initiated.

COMP−4

18

Output regulation voltage monitor terminal (channel 4). When this terminal voltage drops below VREF voltage

(1.5 V) charging to capacitor connected to SCP terminal (pin 23) is initiated.

COMP−5

14

Output regulation voltage monitor terminal (channel 5). When this terminal voltage drops below NONINV

INPUT−5 terminal voltage − 0.55 V, charging to capacitor connected to SCP terminal (pin 23) is initiated.

COMP−6

9

Output regulation voltage monitor terminal (channel 6). When this terminal voltage drops below NONINV

INPUT−6 terminal voltage − 0.55 V, charging to capacitor connected to SCP terminal (pin 23) is initiated.

CT

22

Timing capacitor connection for oscillation frequency setting.

DTC−3

31

Dead-time control input for channel 3. The maximum ON duty cycle for OUTPUT−3 terminal is determined by

comparing the input voltage of this terminal with the oscillator output (triangle wave).

FEEDBACK−1

38

Error amplifier output terminal (channel 1)

FEEDBACK−2

35

Error amplifier output terminal (channel 2)

FEEDBACK−3

32

Error amplifier output terminal (channel 3)

FEEDBACK−4

20

Error amplifier output terminal (channel 4)

FEEDBACK−5

17

Error amplifier output terminal (channel 5)

FEEDBACK−6

12

Error amplifier output terminal (channel 6)

GND

25

Logic ground

INV INPUT−1

39

Error amplifier inverting input terminal (channel 1)

INV INPUT−2

36

Error amplifier inverting input terminal (channel 2)

INV INPUT−3

33

Error amplifier inverting input terminal (channel 3)

INV INPUT−4

19

Error amplifier inverting input terminal (channel 4)

INV INPUT−5

16

Error amplifier inverting input terminal (channel 5)

INV INPUT−6

11

Error amplifier inverting input terminal (channel 6)

MOS DUTY

24

N-channel MOSFET ON duty cycle setting for the synchronous rectification of channel 1 and 4. The MOSFET

ON duty cycle for the synchronous rectification is determined by the resistor value connected between this

terminal and GND.