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MC74LCX16373 Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC74LCX16373 Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev. 6 1 Publication Order Number: MC74LCX16373/D MC74LCX16373 Low−Voltage CMOS 16−Bit Transparent Latch With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The MC74LCX16373 is a high performance, non−inverting 16−bit transparent latch operating from a 2.3 V to 3.6 V supply. The device is byte controlled. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16−bit operation. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX16373 inputs to be safely driven from 5.0 V devices. The MC74LCX16373 contains 16 D−type latches with 3−state 5.0 V−tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH−to−LOW transition of LE. The 3−state outputs are controlled by the Output Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. Features • Designed for 2.3 to 3.6 V VCC Operation • 5.4 ns Maximum tpd • 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic • Supports Live Insertion and Withdrawal • IOFF Specification Guarantees High Impedance When VCC = 0 V • LVTTL Compatible • LVCMOS Compatible • 24 mA Balanced Output Sink and Source Capability • Near Zero Static Supply Current in All Three Logic States (20 mA) Substantially Reduces System Power Requirements • Latchup Performance Exceeds 500 mA • ESD Performance: Human Body Model >2000 V; Machine Model >200 V • These are Pb−Free Devices* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MARKING DIAGRAM TSSOP−48 DT SUFFIX CASE 1201 1 48 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package 1 48 LCX16373G AWLYYWW See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. ORDERING INFORMATION http://onsemi.com |
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