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MC100EP101FAG Scheda tecnica(PDF) 6 Page - ON Semiconductor

Il numero della parte MC100EP101FAG
Spiegazioni elettronici  3.3V / 5V ECL Quad 4?묲nput OR/NOR
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MC100EP101FAG Scheda tecnica(HTML) 6 Page - ON Semiconductor

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MC10EP101, MC100EP101
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Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 14)
−40°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fmax
Maximum Frequency
(See Figure 4. Fmax/JITTER)
> 3
> 3
> 3
GHz
tPLH,
tPHL
Propagation Delay
D to Q, Q
10
100
125
180
225
280
325
380
150
200
250
300
370
400
170
250
300
320
420
450
ps
tSKEW
Within Device Skew
Q, Q
Device to Device Skew (Note 15)
15
50
200
20
50
200
20
50
200
ps
tJITTER
Cycle−to−Cycle Jitter
(See Figure 4. Fmax/JITTER)
0.2
< 1
0.2
< 1
0.2
< 1
ps
tr
tf
Output Rise/Fall Times
Q, Q
(20% − 80%)
100
150
200
120
170
220
150
190
250
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
15.Skew is measured between outputs under identical transitions.
0
100
200
300
400
500
600
700
800
900
1000
0
1000
2000
3000
4000
5000
Figure 4. Fmax/Jitter
FREQUENCY (MHz)
1
2
3
4
5
6
7
8
9
10
(JITTER)
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q
D
Zo = 50 W
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V


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