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MC10EP16DR2G Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC10EP16DR2G Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 11 page MC10EP16, MC100EP16 http://onsemi.com 2 1 2 3 45 6 7 8 Q VEE VCC Figure 1. 8−Lead Pinout (Top View) and Logic Diagram D Q D VBB NC D*, D** ECL Data Inputs Q, Q ECL Data Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply NC No Connect Table 1. PIN DESCRIPTION * Pins will default LOW when left open. ** Pins will default to VCC/2 when left open. PIN FUNCTION EP Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5kW ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg SOIC−8 TSSOP−8 DFN8 Level 1 Level 1 Level 1 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 167 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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