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MC10EL34_06 Datasheet(Scheda tecnica) 6 Page - ON Semiconductor

Numero della parte MC10EL34_06
Dettagli  5V ECL ÷2, ÷4, ÷8 Clock Generation Chip
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Produttore  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC10EL34, MC100EL34
http://onsemi.com
6
There are two distinct functional relationships between the Master Reset and Clock:
CASE 1: If the MR is de−asserted (H−L), while the Clock is still high, the
outputs will follow the first ensuing clock rising edge.
The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal
divider flip−flops will maintain their state during the freeze. The EN is deasserted (LOW), and after the next falling edge
of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela-
tionships.
CASE 2: If the MR is de−asserted (H−L), after the Clock has transitioned low, the
outputs will follow the second ensuing clock rising edge.
CASE 1
CASE 2
Figure 2. Timing Diagrams
CLOCK
OUTPUT
MR
TRR
CLOCK
OUTPUT
MR
TRR
Figure 3. Reset Recovery Time
CLK
Q0
Q1
Q2
EN
Internal Clock
Disabled
Internal Clock
Enabled
MR
CLK
Q0
Q1
Q2
EN
Internal Clock
Disabled
Internal Clock
Enabled
MR




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