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MC10E112FNR2 Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC10E112FNR2 Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 8 page MC10E112, MC100E112 http://onsemi.com 2 VCCO D3 D2 VEE D1 D0 EN 26 27 28 2 3 4 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 56 7 8 9 10 Q3b Q3a Q3b Q3a VCCO Q2b Q2a Q2b Q2a VCC Q1b Q1a Q1b Q1a NC VCCO Q0a Q0b Q0a Q0b VCCO 1 Pinout: 28-Lead PLCC (Top View) *All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram D0 D1 D2 D3 EN Q0a Q0b Q0a Q0b Q1a Q1b Q1a Q1b Q2a Q2b Q2a Q2b Q3a Q3b Q3a Q3b Figure 2. 28−Lead PLCC Pinout Table 1. PIN DESCRIPTION PIN FUNCTION D0 − D3 ECL Data Inputs EN ECL Enable Input Qna, Qnb ECL True Outputs Qna, Qnb ECL Inverting Outputs VCC, VCCO Positive Supply VEE Negative Supply NC No Connect Table 2. Truth Table EN D Q Q L H H L H H H L L L L H H L H L |
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