LM323, LM323A

http://onsemi.com

3

1.0k

Q2

Q1

Q20

210

Q21

100

Q22

6.7V

16k

Q9

Q8

300

Q3

10k

Q4

Q5

Q10

1.0k

Q24

200

Q25

Q27

Q26

3.0k

5.6k

Q16

Q19

10pF

Q23

300

13

0.12

200

Output

50

520

Q12

2.6k

2.0k 3.9k

Q13

Q14

6.0k

Q11

Q6

Q7

40pF

Q15

2.8k

7.2k

840

1.7k

Gnd

Input

2

1.0k

6.0k

Representative Schematic Diagram

Q17

Q18

VOLTAGE REGULATOR PERFORMANCE

The performance of a voltage regulator is specified by its

immunity to changes in load, input voltage, power

dissipation, and temperature. Line and load regulation are

tested with a pulse of short duration (< 100

µs) and are

strictly a function of electrical gain. However, pulse widths

of longer duration (> 1.0 ms) are sufficient to affect

temperature gradients across the die. These temperature

gradients can cause a change in the output voltage, in

addition to changes by line and load regulation. Longer

pulse widths and thermal gradients make it desirable to

specify thermal regulation.

Thermal regulation is defined as the change in output

voltage caused by a change in dissipated power for a

specified time, and is expressed as a percentage output

voltage change per watt. The change in dissipated power

can be caused by a change in either input voltage or the load

current. Thermal regulation is a function of IC layout and

die attach techniques, and usually occurs within 10 ms of

a change in power dissipation. After 10 ms, additional

changes in the output voltage are due to the temperature

coefficient of the device.

Figure 1 shows the line and thermal regulation response

of a typical LM323A to a 20 W input pulse. The variation

of the output voltage due to line regulation is labeled À and

the thermal regulation component is labeled Á. Figure 2

shows the load and thermal regulation response of a typical

LM323A to a 20 W load pulse. The output voltage variation

due to load regulation is labeled À and the thermal

regulation component is labeled Á.

2

1

2

1

Figure 1. Line and Thermal Regulation

Figure 2. Load and Thermal Regulation

t, TIME (2.0 ms/DIV)

1

2

18 V

8.0 V

2

t, TIME (2.0 ms/DIV)

1

2

2.0

0

2