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CS51221EDR16 Scheda tecnica(PDF) 10 Page - ON Semiconductor |
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CS51221EDR16 Scheda tecnica(HTML) 10 Page - ON Semiconductor |
10 / 14 page CS51221 http://onsemi.com 10 Figure 8. The SYNC Pin Generates a Sync Pulse at the Beginning of Each Switching Cycle. CH2: GATE Pin, CH3: RTCT, CH4: SYNC Pin Figure 9. Operation with External Sync. CH2: SYNC Pin, CH3: GATE Pin, CH4: RTCT Pin An external pulse signal can feed to the bidirectional SYNC pin to synchronize the switch frequency. For reliable operation, the sync frequency should be approximately 20% higher than free running IC frequency. As show in Figure 9, when the SYNC pin is triggered by an incoming signal, the IC immediately discharges CT. The GATE signal is turned on once the RTCT pin reaches the valley voltage. Because of the steep falling edge, this valley voltage falls below the regular 1.0 V threshold. However, the RTCT pin voltage is then quickly raised by a clamp. When the RTCT pin reaches the 0.95 V (typ) Valley Clamp Voltage, the clamp is disconnected after a brief delay and CT is charged through RT. DESIGN GUIDELINES Switch Frequency and Maximum Duty Cycle Calculations Oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the discharge time, the internal clock signal sets the Gate output to the low state, thus providing a user selectable maximum duty cycle clamp. Charge and discharge times are determined by following general formulas; tC + RTCT ln (VREF * VVALLEY) (VREF * VPEAK) td + RTCT ln (VREF * VPEAK * IdRT) (VREF * VVALLEY * IdRT) where: tC = charging time; td = discharging time; VVALLEY = valley voltage of the oscillator; VPEAK = peak voltage of the oscillator. Substituting in typical values for the parameters in the above formulas, VREF = 3.3 V, VVALLEY = 1.0 V, VPEAK = 2.0 V, Id = 1.0 mA: tC + 0.57RTCT td + RTCT ln 1.3 * 0.001RT 2.3 * 0.001RT D max + 0.57 0.57 ) In 1.3*0.001RT 2.3 *0.001RT It is noticed from the equation that for the oscillator to function properly, RT has to be greater than 2.3 k. Select RC for Feed Forward Ramp If the line voltage is much greater than the FF pin Peak Voltage, the charge current can be treated as a constant and is equal to VIN/R. Therefore, the volt−second value is determined by: VIN TON + (VCOMP * VFF(d)) R C where: VCOMP = COMP pin voltage; VFF(d) = FF pin discharge voltage. As shown in the equation, the volt−second clamp is set by the VCOMP clamp voltage which is equal to 1.8 V. In Forward or Flyback circuits, the volt−second clamp value is designed to prevent transformers from saturation. In a buck or forward converter, volt−second is equal to VIN TON + VOUT TS n n = transformer turns ratio, which is a constant determined by the regulated output voltage, switching period and transformer turns ration (use 1.0 for buck converter). It is interesting to notice from the aforementioned two equations |
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