CS5165GDWR16 datasheet(7/21 Pages) ONSEMI

Il numero della parte	CS5165GDWR16

Spiegazioni elettronici	5?묪it Synchronous CPU Buck Controller

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CS5165

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PACKAGE PIN DESCRIPTION

PACKAGE PIN #

PIN SYMBOL

FUNCTION

SO−16L

1, 2, 3, 4, 6

VID0−VID4

Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V if left open. VID4

selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is

2.14 V to 3.45 V with 100 mV increments. When VID4 is low (logic zero), the Error Amp

reference voltage 1.34 V to 2.09 V with 50 mV increments.

5

SS

Soft Start Pin. A capacitor from this pin to LGND sets the Soft Start and fault timing.

7

COFF

Off−Time Capacitor Pin. A capacitor from this pin to LGND sets both the normal and

extended off time.

8

ENABLE

Output Enable Input. This pin is internally pulled up to 1.8 V. A logic Low (< 0.8) on this

pin disables operation and places the CS5165 into a low current sleep mode.

9

VCC

Input Power Supply Pin.

10

GATE(H)

High Side Switch FET driver pin.

11

PGND

High current ground for the GATE(H) and GATE(L) pins.

12

GATE(L)

Low Side Synchronous FET driver pin.

13

PWRGD

Power Good Output. Open collector output drives low when VFB is out of regulation. Ac-

tive when ENABLE input is low.

14

LGND

Reference ground. All control circuits are referenced to this pin.

15

COMP

Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error

Amp compensation.

16

VFB

Error Amp, PWM Comparator, and Low VFB Comparator feedback input.

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