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CS5112YDWF24G Scheda tecnica(PDF) 10 Page - ON Semiconductor |
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CS5112YDWF24G Scheda tecnica(HTML) 10 Page - ON Semiconductor |
10 / 13 page CS5112 http://onsemi.com 10 The VOUT/VEA transfer function has a pole at: fp + 1 (pRLOADCOUT) (14) and a zero due to the output capacitor’s ESR at: fz + 1 (2pESR(COUT)) (15) Since the error amplifier reference voltage is 1.25 V, the output voltage must be divided down or attenuated before being applied to the input of the error amplifier. The feedback resistor divider attenuation is: 1.25 V VOUT The error amplifier in the CS5112 is an operational transconductance amplifier (OTA), with a gain given by: GOTA + gmZOUT (16) where: gm + D IOUT DVIN (17) For the CS5112, gm = 2700 mA/V typical. One possible error amplifier compensation scheme is shown in Figure 14. This gives the error amplifier a gain plot as shown in Figure 15. For the error amplifier gain shown in Figure 15, a low frequency pole is generated by the error amplifier output impedance and C1. This is shown by the line AB with a −20 dB/decade slope in Figure 15. The slope changes to zero at point B due to the zero at: fz + 1 (2pR4C1) (18) Figure 14. RC Network Used to Compensate the Error Amplifier (OTA) VOUT VFB1 VFB2 R1 R2 R3 + − 1.25 V M U X SELECT Error Amplifier R4 C1 C2 A pole at point C: fp + 1 (pR4C2) (19) offsets the zero set by the ESR of the output capacitors. An alternative scheme uses a single capacitor as shown in Figure 16, to roll the gain off at a relatively low frequency. Step 9 Finally the watchdog timer period and Power on Reset time is determined by: tDelay + 1.353 CDelayRBIAS (20) Figure 15. Bode Plot of Error Amplifier (OTA) Gain and Modulator Gain Added to the Feedback Resistor Divider Attenuation G −G 0 A B Pole due to error amplifier output impedance and C1 fz = 1/(2πR4C1) fp = 1/(πR4C2) −20 dB/dec error amplifier gain +G C fCO fp = 1/(πRLOADCOUT) modulator gain + feedback resistor divider attenuation fz = 1/(2πESR(COUT)) |
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