74HC74 datasheet(3/8 Pages) ONSEMI

Il numero della parte	74HC74

Spiegazioni elettronici	Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbol

Parameter

Test Conditions

VCC

(V)

Guaranteed Limit

Unit

– 55 to

25_C

v 85_C

v 125_C

VIH

Minimum High−Level Input

Voltage

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

2.0

3.0

4.5

6.0

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

V

VIL

Maximum Low−Level Input

Voltage

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

2.0

3.0

4.5

6.0

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

V

VOH

Minimum High−Level Output

Voltage

Vin = VIH or VIL

|Iout| v 20 mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VIH or VIL |Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.2

3.7

5.2

VOL

Maximum Low−Level Output

Voltage

Vin = VIH or VIL

|Iout| v 20 mA

2.0

4.5

6.0

0.1

V

Vin = VIH or VIL |Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

3.0

4.5

6.0

0.26

0.33

0.4

Iin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

mA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 mA

6.0

2.0

20

80

mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Symbol

Parameter

VCC

(V)

Guaranteed Limit

Unit

– 55 to

25_C

v 85_C

v 125_C

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

3.0

4.5

6.0

15

30

35

4.8

10

24

28

4.0

8.0

20

24

MHz

tPLH,

tPHL

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

2.0

3.0

4.5

6.0

100

75

20

17

125

90

25

21

150

120

30

26

ns

tPLH,

tPHL

Maximum Propagation Delay, Set or Reset to Q or Q

(Figures 2 and 4)

2.0

3.0

4.5

6.0

105

80

21

18

130

95

26

22

160

130

32

27

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

3.0

4.5

6.0

75

30

15

13

95

40

19

16

110

55

22

19

ns

Cin

Maximum Input Capacitance

—

10

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Flip−Flop)*

Typical @ 25°C, VCC = 5.0 V

pF

32

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

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