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SN74GTL2107PWR Scheda tecnica(PDF) 2 Page - Texas Instruments |
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SN74GTL2107PWR Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 10 page www.ti.com SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR SCLS699 – JULY 2006 FUNCTION TABLES(1) INPUTS OUTPUT 1AO/2AO EN1 1BI/2BI (OPEN DRAIN) H L L H H H L X H (1) H = High voltage level, L = Low voltage level INPUTS OUTPUT 3AO/4AO EN2 3BI/4BI (OPEN DRAIN) H L L H H H L X H INPUT OUTPUT 9BI 9AO L L H H INPUTS OUTPUT 10BO1/10BO2 10AI1/10AI2 9BI L L L L H L H L L H H H INPUTS INPUT/OUTPUT OUTPUT 5A/6A 7BO1/7BO2 EN2 5BI/6BI (OPEN DRAIN) H L L H(1) H H L(2) L H H H H L H L(2) L L H H H L L H H L L L(2) H (1) The enable on 7BO1/7BO2 includes a delay that prevents a transient condition (where 5BI/6BI goes from low to high, and the low to high on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs. (2) Open-drain input/output terminal is driven to a logic-low state by an external driver. INPUT/OUTPUT INPUT OUTPUT 11A 11BI 11BO (OPEN DRAIN) L H L L L(1) H H L H (1) Open-drain input/output terminal is driven to a logic-low state by an external driver. 2 Submit Documentation Feedback |
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