MOTOROLA CMOS LOGIC DATA

159

MC14042B

Figure 2. AC Test Circuit and Timing Diagram

(Clock to Output)

NOTE: CL connected to output under test.

20* ns

20 ns

90%

10%

PULSE

GENERATOR 1

PULSE

GENERATOR 2

VDD

16

5

6

4

7

13

14

CLOCK

POLARITY

D0

D1

D2

D3

Q3

Q3

Q2

Q2

Q1

Q1

Q0

Q0

VSS

8

15

1

12

11

9

10

3

2

50%

tWH

20 ns

90%

50%

tsu

th

tPLH

90%

50%

10%

CLOCK INPUT

P.G. 1

DATA INPUT

P.G. 2

Q OUTPUT

* Input clock rise time is 20 ns except for maximum rise time test.