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CAT130011RWI-GT3 Scheda tecnica(PDF) 3 Page - Catalyst Semiconductor |
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CAT130011RWI-GT3 Scheda tecnica(HTML) 3 Page - Catalyst Semiconductor |
3 / 14 page CAT130xx © 2007 Catalyst Semiconductor, Inc. 3 Doc. No. 1121 Rev. A Characteristics subject to change without notice A.C. CHARACTERISTICS (MEMORY) (1) VCC = +2.5V to 5.5V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Min Max Units fSK Clock Frequency DC 2000 kHz tCSS CS Setup Time 50 ns tCSH CS Hold Time 0 ns tCSMIN Minimum CS Low Time 0.25 µs tSKHI Minimum SK High Time 0.25 µs tSKLOW Minimum SK Low Time 0.25 µs tDIS DI Setup Time 100 ns tDIH DI Hold Time 100 ns tPD1 Output Delay to 1 0.25 µs tPD0 Output Delay to 0 0.25 µs tHZ (1) Output Delay to High-Z 100 ns tSV Output Delay to Status Valid 0.25 µs tEW Program/Erase Pulse Width 5 ms tPU (2), (3) Power-up to Ready Mode 1 ms Notes: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50 ns Input Levels 0.4V to 2.4V (4.5V < VCC < 5.5V) Input Levels 0.2VCC to 0.7VCC (2.5V < VCC < 4.5V) Timing Reference Levels 0.8V, 2.0V (4.5V < VCC < 5.5V) Timing Reference Levels 0.5VCC (2.5V < VCC < 4.5V) Output Load Current Source: IOL max / IOH max; CL = 100pF |
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