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74AUP1G885DC Scheda tecnica(PDF) 11 Page - NXP Semiconductors |
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74AUP1G885DC Scheda tecnica(HTML) 11 Page - NXP Semiconductors |
11 / 19 page 74AUP1G885_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 — 26 January 2006 11 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate [1] All typical values are measured at nominal VCC. [2] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(C L × VCC 2 × f o) = sum of the outputs. [3] The condition is VI = GND to VCC. tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B to 2Y see Figure 4 VCC = 0.8 V - 38.9 - ns VCC = 1.1 V to 1.3 V 2.6 10.0 20.5 ns VCC = 1.4 V to 1.6 V 2.6 6.9 11.9 ns VCC = 1.65 V to 1.95 V 2.7 5.7 9.5 ns VCC = 2.3 V to 2.7 V 2.5 4.7 6.9 ns VCC = 3.0 V to 3.6 V 2.4 4.4 6.1 ns Tamb = 25 °C CPD power dissipation capacitance f = 1 MHz [2] [3] VCC = 0.8 V - 2.7 - pF VCC = 1.1 V to 1.3 V - 2.9 - pF VCC = 1.4 V to 1.6 V - 3.0 - pF VCC = 1.65 V to 1.95 V - 3.1 - pF VCC = 2.3 V to 2.7 V - 3.5 - pF VCC = 3.0 V to 3.6 V - 4.1 - pF Table 9: Dynamic characteristics …continued Voltages are referenced to GND (ground=0V; for test circuit see Figure 5 Symbol Parameter Conditions Min Typ [1] Max Unit |
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