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MTV112AN-999 Scheda tecnica(PDF) 11 Page - List of Unclassifed Manufacturers

Il numero della parte MTV112AN-999
Spiegazioni elettronici  8051 Embedded CRT Monitor Controller MASK Version
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Produttore elettronici  ETC2 [List of Unclassifed Manufacturers]
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MTV112AN-999 Scheda tecnica(HTML) 11 Page - List of Unclassifed Manufacturers

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MYSON
TECHNOLOGY
MTV112A
(Rev 1.9)
MTV112A Revision 1.9 05/18/2001
11/20
VCNTH (r) :
V-Freq counter's high bits.
Vovf
= 1
→ V-Freq counter overflows; this bit is cleared by H/W when condition removed.
VF8 :
High bit of V-Freq counter.
VCNTL (r) :
V-Freq counter's low bits.
PCTR0 (w) :
SYNC processor control register 0.
C1, C0 = 1,1
→ Selects CVSYNC as the polarity, Freq and VBLANK source.
= 1,0
→ Selects VSYNC as the polarity, Freq and VBLANK source.
= 0,0
→ Disables composite function (MTV012 compatible mode).
= 0,1
→ H/W auto switches to CVSYNC when CVpre=1 and VSpre=0.
HVsel
= 1
→ Pin #16 is P4.1, pin #17 is P4.0.
= 0
→ Pin #16 is HBLANK, pin #17 is VBLANK.
STOsel = 1
→ Pin #29 is P4.2.
= 0
→ Pin #29 is STOUT.
PREFS = 0
→ Selects 8MHz OSC as H/V presence check and self-test pattern time base.
= 1
→ Selects 12MHz OSC as H/V presence check and self-test pattern time base.
HALFV = 1
→ VBLANK is half frequency output of VSYNC.
HBpl
= 1
→ Negative polarity HBLANK output.
= 0
→ Positive polarity HBLANK output.
VBpl
= 1
→ Negative polarity VBLANK output.
= 0
→ Positive polarity VBLANK output.
PCTR2 (w) :
Self-test pattern generator control.
Selft
= 1
→ Enables generator.
= 0
→ Disables generator.
STbsh = 1
→ 63.5KHz (horizontal) output selected.
= 0
→ 31.75KHz (horizontal) output selected.
Rt1, Rt0= 0,0
→ Positive cross-hatch pattern output.
= 0,1
→ Negative cross-hatch pattern output.
= 1,0
→ Full white pattern output.
= 1,1
→ Full black pattern output.
STF
= 1
→ Enables STOUT output.
= 0
→ Disables STOUT output.
PCTR3 (w) :
HSYNC clamp pulse control register.
ENCLP = 1
→ pin #4 is HCLAMP.
= 0
→ pin #4 is P1.3.
CLPEG = 1
→ Clamp pulse follows HSYNC leading edge.
= 0
→ Clamp pulse follows HSYNC trailing edge.
CLPPO= 1
→ Positive polarity clamp pulse output.
= 0
→ Negative polarity clamp pulse output.
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] X 0.25 µs for 8MHz X’tal selection,or
[(CLPW2:CLPW0) + 1] X 0.167 µs for 12MHz X’tal selection.
EHALFV= 1
→ pin #2 is HALFV.
= 0
→ pin #2 is P1.1.
EHALFV= 1
→ pin #3 is HALFH.
= 0
→ pin #3 is P1.2.
P4OUT (w) :
Port 4 data output value.
P5OUT (r/w) :
Port 5 data input/output value.


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