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CS5334 Scheda tecnica(PDF) 4 Page - Cirrus Logic |
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CS5334 Scheda tecnica(HTML) 4 Page - Cirrus Logic |
4 / 18 page CDB5334/35/60 4 DS194DB3 but inverting the SCLK so that data is valid on the falling edge of SCLK will make the Format 0 inter- face lines match the Format 1 interface lines on the CS8402A. The PLD configures the CS8402A to Format 1 and performs SCLK inversion automati- cally when the DIF1, DIF0 switches on SW1 are set to 00. Digital Interface Format 1 on the CS5334, CS5335, and CS5360 has valid data on the falling edge of SCLK. This interface format matches Format 1 on the CS8402A, so no modification is performed on the digital interface lines. The PLD configures the CS8402A to FORMAT 1 and passes the interface lines from the CS5334, CS5335, or CS5360 through to the CS8402A unchanged when the DIF1, DIF0 switches are set to 01. Digital Interface Format 2 is the I2S compatible mode. It matches Format 4 on the transmitter. The PLD configures the CS8402A to Format 4 and passes the interface lines from the CS5334, CS5335, or CS5360 through to the CS8402A un- changed when the DIF1, DIF0 switches are set to 10. CS8402A MCLK Generation When the CDB5334/35/60 is set up for SLAVE mode, the crystal oscillator (U5) can be 256x, 384x, or 512x Fs. The CS8402A requires a master clock frequency of 128x Fs to operate. The PLD can be configured to divide MCLK_5335 (the os- cillator output) by 2, 3, or 4 to generate MCLK_8402, thus accommodating the various possible frequencies of the oscillator. The switches on SW1 labeled MCLK_S1 and MCLK_S0 select the degree of clock division as defined in Table 3. Decoding PSL bits / Driving LEDs The PLD decodes and displays the Peak Signal Level bits for both High Resolution and Bargraph modes (for detailed information on the PSL bits, see the CS5334/CS5335 and CS5360 datasheets). When the TMODE1 and TMODE2 jumpers, de- fined in Table 2, are set to BARGRAPH, the PLD decodes the PSL bits and drives bargraph LEDs for the left and right channels. When the TMODE1 and TMODE2 jumpers are set to HI RES (High Reso- lution mode), the PLD drives the 7 segment dis- plays for left and right channels. The PLD also provides a Peak Update (PU) signal, which adjusts the rate at which the PSL bits are up- dated. Four settings provide update rates ranging from 42 ms to 2.7 s (for a 48 kHz sample rate). The switches on SW1 labeled PU_S1 and PU_S0 select the PU frequency as shown in Table 3. GROUNDING AND POWER SUPPLY DECOUPLING The CS5334, CS5335, and CS5360 require careful attention to power supply and grounding arrange- ments to optimize performance. Figure 4 shows the recommended power arrangements. The CS5334, CS5335, or CS5360 is positioned over the analog ground plane, near the digital/analog ground plane split, to minimize the distance that the clocks trav- el. The series resistors are present on the clock and data lines to reduce the effects of transient currents when driving a capacitive load in MASTER mode, and to reduce clock overshoot when applying ex- ternal clocks to the ADC in SLAVE mode. This layout technique is used to minimize digital noise and to insure proper power supply match- ing/sequencing. The decoupling capacitors are lo- cated as close to the ADC as possible. Extensive use of ground plane fill on both the analog and dig- ital sections of the evaluation board yield large re- ductions in radiated noise effects. |
Codice articolo simile - CS5334 |
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Descrizione simile - CS5334 |
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