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ISL3685IR Scheda tecnica(PDF) 7 Page - Intersil Corporation |
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ISL3685IR Scheda tecnica(HTML) 7 Page - Intersil Corporation |
7 / 19 page 7 Reference Frequency Counter/Divider BIT DESCRIPTION R(0-14) Least significant bit R(0) to most significant bit R(14) of the divide by R counter. The Reference signal frequency is divided down by this counter and is compared with a divided LO by a phase detector. LO Frequency Counters/Dividers BIT DESCRIPTION A(0-6) Least significant bit A(0) to most significant bit A(6) of a 7-bit Swallow counter and LSB B(0) to MSB B(10) of the 11-bit divider. The LO frequency is divided down by [P*B+A], where P is the Prescaler divider set by bit M(2). This divided signal frequency is compared by a phase detector with the divided Reference signal. B(0-11) Operational Modes BIT DESCRIPTION M(0) (PLL_PE), Phase Lock Loop Power Enable. 1 = Enable, 0 = Power Down. Serial port always on. M(2) Prescaler Select. 0 = 32/33, 1 = 64/65. M(3) M(4) Charge Pump Current Setting M(4) M(3) OUTPUT SINK/SOURCE 0 0 0.25mA 0 1 0.50mA 1 0 0.75mA 1 1 1.00mA M(5) M(6) Charge Pump Sign M(6) M(5) 0 0 Source if LO/ [P*B+A] < Ref/R 0 1 Source if LO/ [P*B+A] > Ref/R M(7) M(8) M(13) LD Pin Multiplex Operation M(13) M(8) M(7) OUTPUT AT PIN LD 0 0 X Lock Detect Operation 0 1 X Short to GND 1 0 X Serial Register Read Back 1 1 0 Ref. Divided by R Waveform 1 1 1 LO Divided by [P*B+A] Waveform M(14) M(15) Charge Pump Operation/Test M(15) M(14) OPERATION/TEST 0 0 Normal Operation 0 1 Charge Pump Constant Current Source 1 0 Charge Pump Constant Current Sink 1 1 High Impedance State ISL3685 |
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