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MC145162 Scheda tecnica(PDF) 7 Page - Motorola, Inc |
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MC145162 Scheda tecnica(HTML) 7 Page - Motorola, Inc |
7 / 24 page MC145162 •MC145162–1 MOTOROLA 7 VH = High voltage level. VL = Low voltage level. *At this point, when both fR and fV are in phase, the output is forced to near mid supply. fR, REFERENCE (OSCinREFERENCE COUNTER) fV, FEEDBACK (fin–TTx COUNTER OR fin–RRx COUNTER) TxPDout OR RxPDout VH VL VH VH VL HIGH IMPEDANCE * Figure 7. Phase Detector/Lock Detector Output Waveforms LD NOTE: The TxPDout and RxPDout generate error pulses during out–of–lock conditions. When locked in phase and fre- quency, the output is high impedance and the voltage at that pin is determined by the low–pass filter capacitor. MCU PROGRAMMING SCHEME The MCU programming scheme is defined in two formats controlled by the ENB input. If the enable signal is high during the serial data transfer, control register/reference frequency programming is selected. If the ENB is low, programming of the transmit and receive counters is selected. During pro- gramming of the transmit and receive counters, both ADin and Din pins can input the data to the transmit and receive counters. Both counters’ data is clocked into the PLL internal shift register at the leading edge of the CLK signal. It is not necessary to reprogram the reference frequency counter/ control register when using the enable signal to program the transmit/receive channels. In programming the control register/reference frequency scheme, the most significant bit (MSB) of the programming word identifies whether the input data is the control word or the reference frequency data word. If the MSB is 1, the input data is the control word (Figure 8). Also see Figure 8 and Table 1 for control register and bit function. If the MSB is 0, the input data is the reference frequency (Figure 9). The reference frequency data word is a 32–bit word con- taining the 12–bit reference frequency data, the 14–bit auxil- iary reference frequency counter information, the reference frequency selection plus, the auxiliary reference frequency counter enable bit (Figure 9). If the AUX REF ENB bit is high, the 14–bit auxiliary refer- ence frequency counter provides an additional phase refer- ence frequency output for the loops. If AUX REF ENB bit is low, the auxiliary reference frequency counter is forced into power–down mode for current saving. (Other power down modes are also provided through the control register per Table 2 and Figure 8.) At the falling edge of the ENB signal, the data is stored in the registers. There are two interfacing schemes for the universal chan- nel mode: the three–pin and the four–pin interfacing schemes. The three–pin interfacing scheme is suited for use with the MCU SPI (serial peripheral interface) (Figure 10), while the four–pin interfacing scheme is commonly used for general I/O port connection (Figure 11). For the three–pin interfacing scheme, the auxiliary data select bit is set to 0. All 32 bits of data, which define both the 16–bit transmit counter and the 16–bit receive counter, latch into the PLL internal register through the data in pins at the leading edge of CLK. See Figures 12 and 13. For the four–pin interfacing scheme, the auxiliary data select bit is set to 1. In this scheme, the 16–bit transmit count- er’s data enters into the ADin pin at the same time as the 16–bit receive counter’s data enters into the Din pin. This si- multaneous entry of the transmit and receive counters causes the programming period of the four–pin scheme to be half that of the three–pin scheme (see Figures 14 and 15). While programming Tx/Rx Channel Counter, the ENB pin must be pulsed to provide falling edge to latch the shifted data after the rising edge of the last clock. Maximum data transfer rate is 500 kbps. NOTE 10 ms should be allowed for initial start–up time for the oscillator to allow all registers to clear and enable programming of new register values. |
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