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AD9396 Scheda tecnica(PDF) 8 Page - Analog Devices |
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AD9396 Scheda tecnica(HTML) 8 Page - Analog Devices |
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8 / 48 page  AD9396 Rev. 0 | Page 8 of 48 Pin Type Pin No. Mnemonic Function Value OUTPUTS 89 DATACK Data Output Clock VDD 87 HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) VDD 85 VSOUT VSYNC Output Clock (Phase-Aligned with DATACK) VDD 86 SOGOUT SOG Slicer Output VDD 84 O/E FIELD Odd/Even Field Output VDD 24, 25, 26, 27 CTL(3-0) Control 3, 2, 1, and 0. VDD REFERENCES 57 FILT Connection for External Filter Components for PLL POWER SUPPLY 80, 76, 72, 67, 45, 33 VD Analog Power Supply and DVI Terminators 3.3 V 100, 90, 10 VDD Output Power Supply 1.8 V to 3.3 V 59, 56, 54 PVDD PLL Power Supply 1.8 V 48, 32, 30 DVDD Digital Logic Power Supply 1.8 V GND Ground 0 V CONTROL 83 SDA Serial Port Data I/O 3.3 V CMOS 82 SCL Serial Port Data Clock 3.3 V CMOS HDCP 49 DDCSCL HDCP Slave Serial Port Data Clock 3.3 V CMOS 50 DDCSDA HDCP Slave Serial Port Data I/O 3.3 V CMOS 51 MCL HDCP Master Serial Port Data Clock 3.3 V CMOS 52 MDA HDCP Master Serial Port Data I/O 3.3 V CMOS DIGITAL VIDEO DATA 35 Rx0+ Digital Input Channel 0 True TMDS 34 Rx0− Digital Input Channel 0 Complement TMDS 38 Rx1+ Digital Input Channel 1 True TMDS 37 Rx1− Digital Input Channel 1 Complement TMDS 41 Rx2+ Digital Input Channel 2 True TMDS 40 Rx2− Digital Input Channel 2 Complement TMDS DIGITAL VIDEO CLOCK INPUTS 43 RxC+ Digital Data Clock True TMDS 44 RxC− Digital Data Clock Complement TMDS DATA ENABLE 88 DE Data Enable 3.3 V CMOS RTERM 46 RTERM Sets Internal Termination Resistance 500 Ω Table 6. Pin Function Descriptions Mnemonic Description INPUTS RAIN0 Analog Input for the Red Channel 0. GAIN0 Analog Input for the Green Channel 0. B B AIN0 Analog Input for the Blue Channel 0. RAIN1 Analog Input for the Red Channel 1. GAIN1 Analog Input for the Green Channel 1. B B AIN1 Analog Input for Blue Channel 1. High impedance inputs that accept the red, green, and blue channel graphics signals, respectively. The three channels are identical and can be used for any colors, but colors are assigned for convenient reference. They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation (see Figure 3 for an input reference circuit). Rx0+ Digital Input Channel 0 True. Rx0− Digital Input Channel 0 Complement. Rx1+ Digital Input Channel 1 True. Rx1− Digital Input Channel 1 Complement. Rx2+ Digital Input Channel 2 True. Rx2− Digital input Channel 2 Complement. These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel rate) from a digital graphics transmitter. |
Codice articolo simile - AD9396 |
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Descrizione simile - AD9396 |
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