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AD9387NK Scheda tecnica(PDF) 8 Page - Analog Devices |
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AD9387NK Scheda tecnica(HTML) 8 Page - Analog Devices |
8 / 12 page AD9387NK Rev. PrA | Page 8 of 12 PCB LAYOUT RECOMMENDATIONS The AD9387NK is a high precision, high speed analog device. For maximum performance, it is important that board layout be optimized. POWER SUPPLY BYPASSING It is recommended that each power supply pin be bypassed with a 0.1 μF capacitor. The exception is when two or more supply pins are adjacent to each other. For these groupings of powers and grounds, it is necessary to have only one bypass capacitor. The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. Avoid placing the capacitor on the opposite side of the PC board from the AD9387NK, as doing so interposes resistive vias in the path. The bypass capacitors should be located between the power plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. Do not make a power connection between the capacitor and the power pin. Placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. It is particularly important to maintain low noise and good stability of PVDD (the PLL supply). Abrupt changes in PVDD can result in similarly abrupt changes in sampling clock phase and frequency. Such changes can be avoided by careful attention to regulation, filtering, and bypassing. It is best practice to provide separate regulated supplies for each of the analog circuitry groups (AVDD and PVDD). It is also recommended that a single ground plane be used for the entire board. Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detri- mental because each separate ground plane is smaller, and long ground loops can result. DIGITAL INPUTS Video and Audio Data Input Signals The digital inputs on the AD9387NK are designed to work with signals ranging from 1.8 V to 3.3 V logic level. Therefore, no extra components need to be added when using 3.3 V logic. Any noise that gets onto the clock input (labeled CLK) trace adds jitter to the system. Therefore, minimize the video clock input (Pin 6, CLK) trace length, and do not run any digital or other high frequency traces near it. Make sure to match the length of the input data signals to optimize data capture, especially for high frequency modes, such as 720p or XGA at 75 Hz and double data rate input formats. Other Input Signals The HPD must be connected to the HDMI connector. A 10 kΩ pull-down resistor to ground is also recommended. The PD/A0 input pin can be connected to GND or supply (through a resistor or a control signal). The device address and power-down polarity are set by the state of the PD/A0 pin when the AD9387NK supplies are applied/enabled. For example, if the PD/A0 pin is low (when the supplies are turned on), then the device address is 0x72 and the power-down is active high. If the PD/A0 pin is high (when the supplies are turned on), the device address is 0x7A and the power down is active low. The SCL and SDA pins should be connected to the I2C master. A pull-up resistor of 2 kΩ to 1.8 V or 3.3 V is recommended. EXTERNAL SWING RESISTOR The external swing resistor must be connected directly to the EXT_SWG pin and ground. The external swing resistor must have a value of 887 Ω (±1% tolerance). Avoid running any high speed ac or noisy signals next to, or close to, the EXT_SWG pin. OUTPUT SIGNALS TMDS Output Signals The AD9387NK has three TMDS data channels (0, 1, and 2) that output signals up to 800 MHz, as well as the TMDS output data clock. To minimize the channel-to-channel skew, make the trace length of these signals the same. Also, these traces need a 50 Ω characteristic impedance and should be routed as 100 Ω differential pairs. Best practice recommends routing these lines on the top PCB layer, avoiding the use of vias. Other Output Signals (non TMDS) DDCSCL and DDCSDA The DDCSCL and DDCSDA outputs need a minimum amount of capacitance loading to ensure the best signal integrity. The DDCSCL and DDCSDA capacitance loading must be less than 50 pF to meet the HDMI compliance specification. The DDCSCL and DDCSDA must be connected to the HDMI connector, and a pull-up resistor to 5 V is required. The pull-up resistor must have a value between 1.5 kΩ and 2 kΩ. INT Pin The INT pin is an output that should be connected to the system microcontroller. A pull-up resistor to 1.8 V or 3.3 V is required for proper operation; the recommended value is 2 kΩ. MCL and MDA The MCL and MDA outputs should be connected to the EEPROM containing the HDCP key (if HDCP is implemented). Pull-up resistors of 2 kΩ are recommended. |
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