AD8106/AD8107

Rev. 0 | Page 8 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

56

57

58

59

54

55

52

53

50

51

60

45

46

47

48

43

44

42

49

41

5

4

3

2

7

6

9

8

1

11

10

16

15

14

13

18

17

20

19

12

CE

RESERVED

CLK

RESERVED

UPDATE

RESERVED

A0

A1

A2

D0

D1

D2

D3

D4

AGND

AVEE

AVCC

AVCC00

AGND00

OUT00

IN08

AGND

IN09

AGND

IN10

AGND

IN11

AGND

IN12

AGND

IN13

AGND

IN14

AGND

IN15

AGND

AVEE

AVCC

AVCC

NC

AD8106/AD8107

16 × 5

80L LQFP

(12mm × 12mm)

TOP VIEW

(PINS DOWN)

0.5mm LEAD PITCH

PIN 1

INDICATOR

Figure 5. 80-Lead Plastic LQFP

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

INxx

Analog Inputs; xx = Channel Numbers 00 through 15.

64 , 66, 68, 70, 72, 74, 76, 78, 1,

3, 5, 7, 9, 11, 13, 15,

58

CLK

Clock, TTL Compatible. Falling edge triggered.

56

UPDATE

Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data

latched when high.

61

RESET

Disable Outputs, Active Low.

60

CE

Chip Enable, Enable Low. Must be low to clock in and latch data.

41, 38, 35, 32, 29

OUTyy

Analog Outputs; yy = Channel Numbers 00 Through 04.

AGND

Analog Ground for Inputs and Switch Matrix.

2, 4, 6, 8, 10, 12, 14, 16, 21, 24, 27,

46, 65, 67, 69, 71, 73, 75, 77

63, 79

DVCC

5 V for Digital Circuitry.

62, 80

DGND

Ground for Digital Circuitry.

17, 22, 45

AVEE

−5 V for Inputs and Switch Matrix.

18, 19, 25, 44

AVCC

+5 V for Inputs and Switch Matrix.

42, 39, 36, 33, 30

AGNDxx

Ground for Output Amp; xx = Output Channel Numbers 00 Through 07. Must be connected.

43, 37, 31, 22

AVCCxx/yy

+5 V for Output Amplifier. Shared by channel numbers xx and yy. Must be connected.

40, 34, 28

AVEExx/yy

−5 V for Output Amplifier. Shared by channel numbers xx and yy. Must be connected.

54

A0

Parallel Data Input, TTL Compatible (Output Select LSB).

53

A1

Parallel Data Input, TTL Compatible (Output Select).

52

A2

Parallel Data Input, TTL Compatible (Output Select MSB).

51

D0

Parallel Data Input, TTL Compatible (Input Select LSB).

50

D1

Parallel Data Input, TTL Compatible (Input Select).

49

D2

Parallel Data Input, TTL Compatible (Input Select).

48

D3

Parallel Data Input, TTL Compatible (Input Select MSB).

47

D4

Parallel Data Input, TTL Compatible (Output Enable).