P89LPC9401 datasheet(19/59 Pages) PHILIPS

Il numero della parte	P89LPC9401

Spiegazioni elettronici	8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 32 segment x 4 LCD driver

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19 / 59 page

P89LPC9401_1

Preliminary data sheet

Rev. 01 — 5 September 2005

19 of 59

Philips Semiconductors

P89LPC9401

8-bit two-clock 80C51 microcontroller with 32 segment

× 4 LCD driver

7.7 CPU Clock (CCLK) wake-up delay

The P89LPC9401 has an internal wake-up timer that delays the clock until it stabilizes

depending on the clock source used. If the clock source is any of the three crystal

selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus

60

µsto100 µs. If the clock source is either the internal RC oscillator, watchdog oscillator,

or external clock, the delay is 224 OSCCLK cycles plus 60

µsto100 µs.

7.8 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

7.9 Low power select

The P89LPC9401 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is

8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power

consumption further. On any reset, CLKLP is logic 0 allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

7.10 Memory organization

The various P89LPC9401 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status

registers, accessible only via direct addressing.

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