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AD7328BRUZ-REEL Scheda tecnica(PDF) 8 Page - Analog Devices |
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AD7328BRUZ-REEL Scheda tecnica(HTML) 8 Page - Analog Devices |
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8 / 36 page  AD7328 Rev. A | Page 8 of 36 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DIN DGND AGND VIN0 VSS REFIN/OUT CS DGND DOUT VDRIVE VIN2 VDD VCC VIN5 VIN4 VIN1 VIN7 VIN6 VIN3 SCLK AD7328 TOP VIEW (Not to Scale) Figure 3. TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7328 and frames the serial data transfer. 2 DIN Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of SCLK (see the Registers section). 3, 19 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7328. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 4 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7328. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 5 REFIN/OUT Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the AD7328. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor should be placed on the reference pin. Alternatively, the internal reference can be disabled and an external reference applied to this input. On power-up, the external reference mode is the default condition (see the Reference section). 6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. 7, 8, 14, 13, 9, 10, 12, 11 VIN0 to VIN7 Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold. The analog input channel for conversion is selected by programming the Channel Address Bit ADD2 through Bit ADD0 in the control register. The inputs can be configured as eight single-ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and Bit Mode 0, in the control register. The input range on each input channel is controlled by program- ming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each analog input channel when a +2.5 V reference voltage is used (see the Reference section). 15 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. 16 VCC Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7328. This supply should be decoupled to AGND. Specifications apply from VCC = 4.75 V to 5.25 V. 17 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VCC, but it should not exceed VCC by more than 0.3 V. 18 DOUT Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data. The data is provided MSB first (see the Serial Interface section). 20 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7328. This clock is also used as the clock source for the conversion process. |
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