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AD7324BRUZ-REEL7 Scheda tecnica(PDF) 7 Page - Analog Devices

Il numero della parte AD7324BRUZ-REEL7
Spiegazioni elettronici  4-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

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AD7324
Rev. 0 | Page 7 of 36
TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25, VREF = 2.5 V to 3.0 V Internal/External,
TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted.1
Table 3.
Limit at TMIN, TMAX
Description
Parameter
VCC < 4.75 V
VCC = 4.75 V to 5.25 V
Unit
VDRIVE ≤ VCC
fSCLK
50
50
kHz min
14
20
MHz max
tCONVERT
16 × tSCLK
16 × tSCLK
ns max
tSCLK = 1/fSCLK
tQUIET
75
60
ns min
Minimum time between end of serial read and next falling edge of CS
t1
12
5
ns min
Minimum CS pulse width
t22
25
20
ns min
CS to SCLK setup time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
45
35
ns min
Unipolar input range (0 V to 10 V)
t3
26
14
ns max
Delay from CS until DOUT three-state disabled
t4
57
43
ns max
Data access time after SCLK falling edge
t5
0.4 × tSCLK
0.4 × tSCLK
ns min
SCLK low pulse width
t6
0.4 × tSCLK
0.4 × tSCLK
ns min
SCLK high pulse width
t7
13
8
ns min
SCLK to data valid hold time
t8
40
22
ns max
SCLK falling edge to DOUT high impedance
10
9
ns min
SCLK falling edge to DOUT high impedance
t9
4
4
ns min
DIN setup time prior to SCLK falling edge
t10
2
2
ns min
DIN hold time after SCLK falling edge
tPOWER-UP
750
750
ns max
Power up from autostandby
μs max
500
500
Power up from full shutdown/autoshutdown mode, internal reference
25
25
μs typ
Power up from full shutdown/autoshutdown mode, external reference
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2 When using VCC = 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to
50:50.
ADD1
12
34
5
13
14
15
16
WRITE
REG
SEL1
REG
SEL2
LSB
MSB
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
t2
t6
t4
t9
t10
t3
t7
t5
t8
t1
tQUIET
tCONVERT
SCLK
CS
DOUT
THREE-
STATE
THREE-STATE
DIN
ZERO
2 IDENTIFICATION BITS
DON’T
CARE
Figure 2. Serial Interface Timing Diagram


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