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CS5303 Scheda tecnica(PDF) 5 Page - ON Semiconductor |
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CS5303 Scheda tecnica(HTML) 5 Page - ON Semiconductor |
5 / 19 page CS5303 http://onsemi.com 5 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8 V < VCCH < 20 V; CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 53.6 k, CCOMP = 0.1 μF, CREF = 0.1μF, DAC Code 10000, CVCC = 1.0 μF, ILIM ≥ 1 V;unless other- wise specified) Characteristic Test Conditions Min Typ Max Unit PWM Comparators Minimum Pulse Width Measured from CSx to GATE(H) V(VFB) = V(CSREF) = 1.0 V, V(COMP) = 1.5 V 60 mV step applied between VCSX and VCREF − 350 515 ns Channel Start Up Offset V(CS1) = V(CS2) = V(CS3) = V(VFB) = 0.3 V(CSREF) = 0 V; Measure V(COMP) when GATE1(H), 2(H), 3(H) switch high 0.4 0.5 − V Gate(H) and Gate(L) High Voltage (AC) Note 4 Measure VCCLX − Gate(L) or VCCHX − Gate(H) − 0 1.0 V Low Voltage (AC) Note 4, Measure Gate(L) or Gate(H) − 0 0.5 V Rise Time Gate(H)x 1.0 V < GATE < 8.0 V; VCCHX = 10 V − 35 80 ns Rise Time Gate(L)x 1.0 V < GATE < 8.0 V; VCCLX = 10 V − 35 80 ns Fall Time Gate(H)x 8.0 V > GATE > 1.0 V; VCCHX = 10 V − 35 80 ns Fall Time Gate(L) 8.0 V > GATE > 1.0 V; VCCLX = 10 V − 35 80 ns Gate(H) to Gate(L) Delay Gate(H) < 2.0 V, Gate(L) > 2 V 30 65 110 ns Gate(L) to Gate(H) Delay Gate(L) < 2.0 V, Gate(H) > 2 V 30 65 110 ns GATE Pull−down Force 100 μA into Gate Driver with no power applied to VCCHX and VCCLX = 2 V. − 1.2 1.6 V Oscillator Switching Frequency Measure any phase (ROSC = 53.6 k) 220 250 280 kHz Switching Frequency Note 4 Measure any phase (ROSC = 32.4 k) 300 400 500 kHz Switching Frequency Note 4 Measure any phase (ROSC = 16.2 k) 600 800 1000 kHz ROSC Voltage − − 1.00 − V Phase Delay − 105 120 135 deg Adaptive Voltage Positioning VDRP Output Voltage to DACOUT Offset CS1 = CS2 = CS3 = CSREF, VFB = COMP Measure VDRP − COMP −20 − 20 mV Maximum VDRP Voltage |(CS1 = CS2 = CS3) − CREF| = 50 mV, VFB = COMP, Measure VDRP − COMP 360 465 570 mV Current Sense Amp to VDRP Gain − 2.4 3.0 3.8 V/V Current Sensing and Sharing CS1−CS3 Input Bias Current V(CSx) = V(CSREF) = 0 V − 0.2 2.0 μA CSREF Input Bias Current − − 0.6 6.0 μA Current Sense Amplifiers Gain − 3.8 4.3 4.8 V/V Current Sense Amp Mismatch (The sum of offset and gain errors) Note 4 0 ≤ (CSx − CSREF) ≤ 50 mV −5.0 − 5.0 mV Current Sense Amplifiers Input Common Mode Range Limit Note 4 7 V < VCCLL1 < 12 V 0 − VCCLL1 − 2 V Current Sense Input to ILIM Gain 0.25 V < ILIM < 1.20 V 5.0 6.5 8.0 V/V Current Limit Filter Slew Rate Note 4 7.5 15.0 40.0 mV/μs 4. Guaranteed by design. Not tested in production. |
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