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FAN4113 Scheda tecnica(PDF) 8 Page - Fairchild Semiconductor |
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FAN4113 Scheda tecnica(HTML) 8 Page - Fairchild Semiconductor |
8 / 10 page Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Fairchild has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: • Include 6.8 µF and 0.01µF ceramic capacitors • Place the 6.8 µF capacitor within 0.75 inches of the power pin • Place the 0.01 µF capacitor within 0.1 inches of the power pin • Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance • Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts shown in Figure 6 for more information. Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of this device: Evaluation board schematics and layouts are shown in Figure 5 and Figure 6. Figure 5: Evaluation Board Schematic Eval Bd Description Products KEB011 Single Channel, Dual Supply, FAN4113IP5 5 and 6 lead SC70 DATA SHEET FAN4113 8 REV. 1 October 2001 |
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