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ADV7391BCPZ-REEL Scheda tecnica(PDF) 9 Page - Analog Devices |
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ADV7391BCPZ-REEL Scheda tecnica(HTML) 9 Page - Analog Devices |
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9 / 96 page  ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 9 of 96 TIMING DIAGRAMS The following abbreviations are used in Figure 2 to Figure 9. • t9 = Clock high time • t10 = Clock low time • t11 = Data setup time • t12 = Data hold time • t13 = Control output access time • t14 = Control output hold time In addition, refer to Table 30 for the ADV7390/ADV7391 input configuration and Table 31 for the ADV7392/ADV7393 input configuration. t9 CLKIN t10 CONTROL OUTPUTS HSYNC VSYNC Cr2 Cb2 Cr0 Cb0 IN MASTER/SLAVE MODE IN SLAVE MODE Y0 Y1 Y2 PIXEL PORT CONTROL INPUTS t12 t11 t13 t14 Figure 2. SD Input, 8-/10-Bit 4:2:2 YCrCb (Input Mode 000) IN MASTER/SLAVE MODE IN SLAVE MODE CLKIN CONTROL OUTPUTS t9 t10 Cr2 Cb2 Cr0 Cb0 Y0 Y1 Y2 Y3 t12 t14 t11 t13 HSYNC VSYNC CONTROL INPUTS PIXEL PORT PIXEL PORT Figure 3. SD Input, 16-Bit 4:2:2 YCrCb (Input Mode 000) |
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