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ADF4108BCPZ Scheda tecnica(PDF) 4 Page - Analog Devices |
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ADF4108BCPZ Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 20 page ADF4108 Rev. 0 | Page 4 of 20 Parameter B Version1 B Chips2 (Typ) Unit Test Conditions/Comments NOISE CHARACTERISTICS Normalized Phase Noise Floor9 −219 −219 dBc/Hz typ Phase Noise Performance10 @ VCO output 7900 MHz Output11 −81 −81 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency Spurious Signals 7900 MHz Output11 –61 –61 dBc typ @ 1 MHz offset and 1 MHz PFD frequency 1 Operating temperature range (B version) is –40°C to +85°C. 2 The B chip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 AVDD = DVDD = 3.3 V. 5 AC coupling ensures AVDD/2 bias. 6 Guaranteed by design. Sample tested to ensure compliance. 7 TA = 25°C; AVDD = DVDD = 3.3 V; P = 32; RFIN = 8 GHz, fPFD = 200 kHz, REFIN = 10 MHz. 8 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz. 9 This value can be used to calculate phase noise for any application. Use the formula –219 + 10 log(fPFD) + 20 logN to calculate in-band phase noise performance as seen at the VCO output. The value given is the lowest noise mode. 10 The phase noise is measured with the EVAL-ADF4108EB1 evaluation board, with the Hittite HMC506LP4 VCO. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 11 fREFIN = 10 MHz; fPFD = 1 MHz; fRF = 7900 MHz; N = 7900; loop B/W = 50 kHz, VCO = HMC506LP4, spurs are dominated by the leakage current on the tuning port of the HMC506LP4 VCO. |
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