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SN74GTL2006PWRE4 Scheda tecnica(PDF) 2 Page - Texas Instruments |
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SN74GTL2006PWRE4 Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 10 page SN74GTL2006 13BIT GTL/GTL/GTL+ TO LVTTL TRANSLATOR SCES619 – DECEMBER 2004 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Function Tables INPUTS OUTPUTS INPUTS 1BI/2BI/3BI/4BI/9BI OUTPUTS 1AO/2AO/3AO/4AO/9AO L L H H INPUT 8AI OUTPUT 8BO INPUT 8AI OUTPUT 8BO L L H H INPUTS OUTPUTS 10BO1/10BO2 10AI1/10AI2 9BI OUTPUTS 10BO1/10BO2 L L L L HL H LL H H H INPUTS INPUTS/OUTPUTS 5A/6A OUTPUTS INPUTS 5BI/6BI 5A/6A (OPEN DRAIN) OUTPUTS 7BO1/7BO2 L L H† H L‡ L H H H † The enable on 7BO1/7BO2 includes a delay that prevents a transient condition (when 5BI/6BI goes from low to high, and the low to high on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs. ‡ Open-drain input/output terminal is driven to a logic-low state by an external driver. INPUT INPUT/OUTPUT 11A OUTPUT INPUT 11BI 11A (OPEN DRAIN) OUTPUT 11BO L H L L L‡ H H L H ‡ Open-drain input/output terminal is driven to a logic-low state by an external driver. |
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