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ML2201-XXX Scheda tecnica(PDF) 3 Page - OKI electronic componets |
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ML2201-XXX Scheda tecnica(HTML) 3 Page - OKI electronic componets |
3 / 20 page FEDL2201-01 1Semiconductor ML2201–XXX 3/20 PIN DESCRIPTION Pin No. Pin Name I/O Description 1 ST I The playback trigger pin. The number of pulses input to the PI pin, while this pin is held “L”, determines the Phrase Address for playback. At the ST’s rising edge, the phrase address data is loaded into the LSI and playback starts. When no pulse input to PI occurs while this pin is held “L”, the LSI recognizes it as the “Stop Code” that results in stopping playback. 2 PI I The address input pin. The number of pulses input to this pin, while the ST pin is held “L”, determines the Phrase Address for playback. When 32 pulses are input, the internal counter returns to its initial value, “0”. 3 GND — The ground pin. 4AOUT O The analog output pin. Configured as N-MOS open drain, analog signal is output in the form of change in output (attraction) current. While the PDWN pin being held “H”, this pin is sustained at 1/2 level and thus the current keeps on flowing. When shifting to standby state and shifting back to ready state from standby, the pop-noise canceller is put to work. 5V DD — The power supply pin. Insert a 0.1 µF bypass capacitor between this pin and the GND pin. 6XT I The external clock input pin. The ceramic resonator connection pin for ceramic oscillation option under development. 7 XT O Keep this pin open. The LSI’s operations may become unstable if this pin includes any capacitive component. The ceramic resonator connection pin for ceramic oscillation option under development. 8 PDWN I The power down pin. The LSI stays standby state while the pin being held “L”. |
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