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AD9911BCPZ-REEL7 Scheda tecnica(PDF) 11 Page - Analog Devices |
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AD9911BCPZ-REEL7 Scheda tecnica(HTML) 11 Page - Analog Devices |
11 / 44 page AD9911 Rev. 0 | Page 11 of 44 Pin No. Mnemonic I/O Description 6, 10, 12, 16, 28, 32 NC N/A No Connection. Analog Devices recommends leaving these pins floating. 40, 41, 42, 43 P0, P1, P2, P3 I These data pins are used for modulation (FSK, PSK, ASK), start/stop for the sweep accumulator, and ramping up/down the output amplitude. Any toggle of these data inputs is equivalent to an I/O_UPDATE. The data is synchronous to the SYNC_CLK (Pin 54). The data inputs must meet the set-up and hold time requirements to the SYNC_CLK. This guarantees a fixed pipeline delay of data to the DAC output; otherwise, a ±1 SYNC_CLK period of uncertainty occurs. The functionality of these pins is controlled by profile pin configuration (PPC) bits in Register FR1 <12:14>. 46 I/O_UPDATE I A rising edge triggers data transfer from the I/O port buffer to active registers. I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the set-up and hold time requirements to the SYNC_CLK to guarantee a fixed pipeline delay of data to DAC output. If not, a ±1 SYNC_CLK period of uncertainty occurs. The minimum pulse width is one SYNC_CLK period. 47 CS I The active low chip select allows multiple devices to share a common I/O bus (SPI). 48 SCLK I Data Clock for I/O Operations. Data bits are written on the rising edge of SCLK and read on the falling edge of SCLK. 49 DVDD_I/O I 3.3 V Digital Power Supply for SPI Port and Digital I/O. 50 SDIO_0 I/O Data pin SDIO_0 is dedicated to the I/O port only. 51, 52, 53 SDIO_1, SDIO_2, SDIO_3 I/O Data pins SDIO_1:3 can be used for the I/O port or to initiate a ramp up/ramp down (RU/RD) of the DAC output amplitude. 54 SYNC_CLK O The SYNC_CLK, which runs at ¼ the system clock rate, can be disabled. I/O_UPDATE and profile changes (Pin 40 to Pin 43) are synchronous to the SYNC_CLK. To guarantee a fixed pipeline delay of data to DAC output, I/O_UPDATE and profile changes (Pin 40 to Pin 43) must meet the set-up and hold time requirements to the rising edge of SYNC_CLK. If not, a ±1 SYNC_CLK period of uncertainty exists. |
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