24-Bit, 625 kSPS, 109 dB

Σ-Δ ADC

with On-Chip Buffers, Serial Interface

AD7763

Rev. 0

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FEATURES

120 dB dynamic range at 78 kHz output data rate

109 dB dynamic range at 625 kHz output data rate

112 dB SNR at 78 kHz output data rate

107 dB SNR at 625 kHz output data rate

625 kHz maximum fully filtered output word rate

Programmable oversampling rate (32× to 256×)

Flexible serial interface

Fully differential modulator input

On-chip differential amplifier for signal buffering

Low-pass finite impulse response (FIR) filter with default

or user-programmable coefficients

Overrange alert bit

Digital offset and gain correction registers

Low power and power-down modes

Synchronization of multiple devices via SYNC pin

APPLICATIONS

Data acquisition systems

Vibration analysis

Instrumentation

FUNCTIONAL BLOCK DIAGRAM

AD7763

AGND

MCLK

DGND

DECAPA

DECAPB

MCLKGND

SYNC

RESET

SH2:0

ADR2:0

CDIV

CONTROL LOGIC

I/O

OFFSET AND GAIN

REGISTERS

DIFF

MULTIBIT

Σ-Δ

MODULATOR

RECONSTRUCTION

REFGND

FIR FILTER

ENGINE

PROGRAMMABLE

DECIMATION

BUF

Figure 1.

GENERAL DESCRIPTION

The AD7763 high performance, 24-bit, Σ-Δ analog-to-digital

converter (ADC) combines wide input bandwidth and high

speed with the benefits of Σ-Δ conversion, as well as performance

of 107 dB SNR at 625 kSPS, making it ideal for high speed data

acquisition. A wide dynamic range, combined with significantly

reduced antialiasing requirements, simplifies the design process.

An integrated buffer to drive the reference, a differential ampli-

fier for signal buffering and level shifting, an overrange flag,

internal gain and offset registers, and a low-pass, digital FIR

filter make the AD7763 a compact, highly integrated data

acquisition device requiring minimal peripheral component

selection. In addition, the device offers programmable

decimation rates and a digital FIR filter, which can be user-

programmed to ensure that its characteristics are tailored for the

user’s application. The AD7763 is ideal for applications demanding

high SNR without necessitating the design of complex, front-

end signal processing.

The differential input is sampled at up to 40 MSPS by an analog

modulator. The modulator output is processed by a series

of low-pass filters, the final filter having default or user-

programmable coefficients. The sample rate, filter corner

frequencies, and output word rate are set by a combination of

the external clock frequency and the configuration registers of

the AD7763.

The reference voltage supplied to the AD7763 determines the

analog input range. With a 4 V reference, the analog input range

is ±3.2 V differential-biased around a common mode of 2 V.

This common-mode biasing can be achieved using the on-chip

differential amplifiers, further reducing the external signal

conditioning requirements.

The AD7763 is available in an exposed paddle, 64-lead TQFP_EP

and is specified over the industrial temperature range from

−40°C to +85°C.

Table 1. Related Devices

Part No.

Description

AD7760

24-bit, 2.5 MSPS, 100 dB Σ-Δ, parallel interface

AD7762

24-bit, 625 kSPS, 109 dB Σ-Δ, parallel interface