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74LVC2G74DP Scheda tecnica(PDF) 8 Page - NXP Semiconductors |
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74LVC2G74DP Scheda tecnica(HTML) 8 Page - NXP Semiconductors |
8 / 20 page 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 8 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 12. Dynamic characteristics Table 10: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +85 °C [1] tPHL, tPLH propagation delay CP to Q, Q see Figure 6 VCC = 1.65 V to 1.95 V 1.5 6.0 13.4 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.1 ns VCC = 2.7 V 1.0 3.5 7.1 ns VCC = 3.0 V to 3.6 V 1.0 3.5 [2] 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 ns SD to Q, Q see Figure 7 VCC = 1.65 V to 1.95 V 1.5 6.0 12.9 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 ns VCC = 2.7 V 1.0 3.5 7.0 ns VCC = 3.0 V to 3.6 V 1.0 3.0 [2] 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 ns RD to Q, Q see Figure 7 VCC = 1.65 V to 1.95 V 1.5 5.0 12.9 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 ns VCC = 2.7 V 1.0 3.5 7.0 ns VCC = 3.0 V to 3.6 V 1.0 3.0 [2] 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 ns tW pulse width clock CP HIGH or LOW see Figure 6 VCC = 1.65 V to 1.95 V 6.2 - - ns VCC = 2.3 V to 2.7 V 2.7 - - ns VCC = 2.7 V 2.7 - - ns VCC = 3.0 V to 3.6 V 2.7 1.3 [2] -ns VCC = 4.5 V to 5.5 V 2.0 - - ns set SD (LOW) and reset RD (LOW) see Figure 7 VCC = 1.65 V to 1.95 V 6.2 - - ns VCC = 2.3 V to 2.7 V 2.7 - - ns VCC = 2.7 V 2.7 - - ns VCC = 3.0 V to 3.6 V 2.7 1.6 [2] -ns VCC = 4.5 V to 5.5 V 2.0 - - ns |
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