MOTOROLA CMOS LOGIC DATA

MC14538B

2

Characteristic

Symbol

VDD

Vdc

– 55

_C

25

_C

125

_C

Unit

Characteristic

Symbol

DD

Vdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

VOL

5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

0.05

0.05

0.05

Vdc

“1” Level

Vin = 0 or VDD

VOH

5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.95

9.95

14.95

—

—

—

Vdc

Input Voltage

“0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

1.5

3.0

4.0

Vdc

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3.5

7.0

11

—

—

—

Vdc

Output Drive Current

(VOH = 2.5 Vdc)

Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1.7

– 0.36

– 0.9

– 2.4

—

—

—

—

mAdc

(VOL = 0.4 Vdc)

Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL

5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.36

0.9

2.4

—

—

—

mAdc

Input Current, Pin 2 or 14

Iin

15

—

±0.05

—

±0.00001

±0.05

—

±0.5

µAdc

Input Current, Other Inputs

Iin

15

—

±0.1

—

±0.00001

±0.1

—

±1.0

µAdc

Input Capacitance, Pin 2 or 14

Cin

—

—

—

—

25

—

—

—

pF

Input Capacitance, Other Inputs

(Vin = 0)

Cin

—

—

—

—

5.0

7.5

—

—

pF

Quiescent Current

(Per Package)

Q = Low, Q = High

IDD

5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—

150

300

600

µAdc

Quiescent Current, Active State

(Both) (Per Package)

Q = High, Q = Low

IDD

5.0

10

15

—

—

—

2.0

2.0

2.0

—

—

—

0.04

0.08

0.13

0.20

0.45

0.70

—

—

—

2.0

2.0

2.0

mAdc

**Total Supply Current at an

external load capacitance (CL) and

at external timing network (RX, CX)

IT

5.0

10

IT = (3.5 x 10–2) RXCXf + 4CXf + 1 x 10–5 CLf

IT = (8.0 x 10–2) RXCXf + 9CXf + 2 x 10–5 CLf

IT = (1.25 x 10–1) RXCXf + 12CXf + 3 x 10–5 CLf

where: IT in µA (one monostable switching only),

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

** The formulas given are for the typical characteristics only at 25

_C.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,

precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance

circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must

be left open.